Peripheral Clock Selection register
| PCLKDIV | Selects the divide value for the clock used for all APB peripherals. 0 = The divider is turned off., no clock will be provided to APB peripherals… 1 = The input clock is divided by 1 to produce the APB peripheral clock. 2 = The input clock is divided by 2 to produce the APB peripheral clock. 3 = The input clock is divided by 3 to produce the APB peripheral clock. … 31 = The input clock is divided by 31 to produce the APB peripheral clock. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |